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Online Digital Verification Engineer Test

Topics Covered

  • SVA Basics
  • ASIC Verification Basics
  • GLS Basics
  • SDF in Gate Level Simulations
  • X Propagation
  • Zero-Delay Loops
  • Zero-Delay Simulation Basics
  • Condition Coverage

Useful for hiring

  • Digital Verification Engineer
  • Design and Verification Engineer

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Given are a few reasons for limiting the use of immediate assertions in RTL combinational blocks. Which of the following reasons are correct?

Note: There can be multiple correct answers to this question.

    • The immediate assertions are not applicable in GLS

    • If inputs are noisy, there are chances of false errors for zero-time glitches

    • RTL simulation is degraded if assertion coverage collection enabled


You need to do due diligence on the efficiency of the verification implementation. Which of the following are appropriate measures of checking the efficiency?

Note: There can be multiple correct answers to this question.

    • All the legal states in an FSM has been exercised.

    • All the paths within the block have been exercised.

    • All the statements of the RTL code have been exercised.


A Physical Designer by mistake has placed timing exception which includes a false path and a few multi-cycle paths during Placement and Routing. How many of the following analysis will be able to detect this issue during the verification process?

A. RTL Simulation
B. Static Timing Analysis
C. Timing GLS

    • 0

    • 1

    • 2

    • 3

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